Computers
Data movement becomes the new chip performance bottleneck
An Arteris executive argues that data movement—not raw compute—is becoming the key performance constraint in AI chips, chiplets and physical AI.
Semiconductor performance is increasingly constrained not by how much compute or memory a system has, but by how efficiently data can move between its components. That is the central argument in a [TechRadar](https://www.techradar.com/pro/data-movement-is-the-new-performance-battleground-in-semiconductor-design) Pro Perspectives essay from an Arteris vice president of product management and marketing.
The shift is especially visible in AI accelerators, advanced SoCs, chiplet-based systems and physical AI applications such as robotics, industrial automation and intelligent vehicles. Adding CPUs, GPUs, DSPs and specialized engines does not guarantee proportional performance gains: compute units can remain idle when bandwidth allocation, routing or communication contention prevents data from reaching them efficiently.
That problem is more severe in physical AI systems, where sensors, processors and actuators operate in real-time feedback loops. Unpredictable latency can destabilize control algorithms, reduce accuracy or force designers to add compute capacity simply to compensate for the lack of bounded latency and guaranteed behavior.
Inside a chip, the communication fabric must handle very different traffic types at the same time: high-bandwidth AI streams, cache and coherency traffic, latency-sensitive control messages and safety signaling. The essay argues that best-effort arbitration is insufficient for these workloads. Quality of service, traffic isolation, bounded latency and determinism have become architectural requirements, with the interconnect acting as an active policy-enforcement component rather than a passive path for bits.
AI also creates irregular access patterns, asymmetric traffic and distributed computation across specialized engines. Data replication, synchronization and inefficient sharing can consume power and add latency, eroding the gains from heterogeneous compute. In data centers, the challenge expands as processors combine hundreds of compute and accelerator instances with reticle-scale integration, chiplets and multiple stacks of high-bandwidth memory.
Chiplets turn the issue into a system-level design problem. Cross-die communication costs more energy per bit and adds latency compared with on-die transfers, making topology, hierarchy, coherency, protocol selection and physical constraints central to partitioning decisions. A design that divides functionality across dies without planning the resulting data flows can increase complexity instead of reducing it.
The proposed response is deliberate, physically aware interconnect design: synthesize connectivity from traffic and layout constraints, explore floorplans and topologies before physical constraints harden, and maintain consistent architectural, software, verification and implementation views from a unified system description. The essay’s conclusion is direct: as AI systems move into the physical world, competitive performance will depend as much on predictable data paths as on raw processing capacity.